1. Field of the Invention
The present invention relates generally to a floating-gate structure of a non-volatile semiconductor memory device and, more particularly, to a self-aligned floating-gate structure having a high coupling ratio for flash memory device.
2. Description of Related Art
For a non-volatile semiconductor memory device, an efficient device isolation is required in order to eliminate the interference of nearby semiconductor devices. Basically, there are two kinds of device isolation Technologies: local oxidation of silicon (LOCOS) and shallow trench isolation (STI), in which the STI technology is often used for a minimum feature size smaller than 0.3 μm. For a non-volatile semiconductor memory device, a floating-gate layer is in general extended over nearby STI regions to increase the surface area of the floating-gate layer with respect to a control-gate layer in order to increase the coupling ration. For a NAND-type array, the coupling ratio of the floating-gate layer becomes a major factor to decrease the applied control-gate voltage for programming and erasing between the floating-gate layer and the semiconductor substrate. Therefore, the floating-gate structure is very important for a scaled NAND-type flash memory array.
FIG. 1 shows a method of forming a floating-gate structure for fabricating a high-density NAND-type array, as presented in a paper entitled “Advanced Flash Memory Technology and Trends for File Storage Application” published in IEEE IEDM 2000 Tech. Dig., pp. 763, in which a multilayer masking structure including from top to bottom a first masking silicon-nitride layer 103, a first polycrystalline-silicon layer 102, and a tunneling-oxide layer 101 is formed on a p-type semiconductor substrate 100 and is patterned by a first masking photoresist step (not shown) to form shallow trenches, as shown in FIG. 1A; a planarized field-oxide layer 104a is formed to fill up each gap between the patterned first masking silicon-nitride layers 103a by using chemical-mechanical polishing (CMP) and the first masking silicon-nitride layers 103a are then removed by anisotropic dry etching, and thereafter, a second polycrystalline-silicon layer 105 (not shown) is deposited and is then planarized by CMP to form a planarized second polycrystalline-silicon layer 105a, as shown in FIG. 1B; a second masking silicon-nitride layer 106 (not shown) is formed over the planarized second polycrystalline-silicon layer 105a and a second masking photoresist step (not shown) is then applied to pattern the second masking silicon-nitride layer 106, a sidewall silicon-nitride spacer 107a is then formed over each sidewall of the patterned second masking silicon-nitride layers 106a, and thereafter, the planarized second polycrystalline-silicon layer 105a between nearby sidewall silicon-nitride spacers 107a is removed, as shown in FIG. 1C; the patterned second masking silicon-nitride layers 106a and the sidewall silicon-nitride spacers 107a are selectively removed, an intergate-dielectric (ONO) layer 108 is then deposited over the planarized second polycrystalline-silicon layers 105b and the exposed planarized field-oxide layers 104a, a planarized third polycrystalline-silicon layer 109a is formed over the intergate-dielectric layer 108 by using CMP, and subsequently, a tungsten-disilicide (WSi2) layer 110 is formed over the planarized third polycrystalline-silicon layer 109a, as shown in FIG. 1D. It is clearly seen that two critical masking photoresist steps are required to form FIG. 1D, especially the second masking photoresist step is critical and will result in misalignment problem for each scaled flash cell. Moreover, two right corners of the planarized second polycrystalline-silicon layer 105a may result in reliability problems due to the corner field emission effect.
FIG. 2 shows another method of forming a floating-gate structure for fabricating a high-density NAND-type array, as presented in a paper entitled “a 0.15 μm NAND Flash Technology with 0.11 μm2 Cell Size for 1 Gbit Flash memory” published in IEEE IEDM 2000 Tech. Dig., pp 767, in which a similar multilayer masking structure as FIG. 1A is formed over a p-type semiconductor substrate 100 and is patterned by a first masking photoresist step (non shown) to form shallow trenches, and a planarized field-oxide layer 104a is formed to fill up each gap between the patterned first masking silicon-nitride layers 103a, as shown in FIG. 2A; the patterned first masking silicon-nitride layers 103a are then removed by hot-phosphoric acid and a planarized second polycrystalline-silicon layer 111a (non shown) is formed over the patterned first polycrystalline-silicon layers 102a and the exposed planarized field-oxide layers 104a by using CMP, a second masking photoresist step (not shown) is applied to pattern the planarized second polycrystalline-silicon layer 111a and a anisotropic dry etching is performed to form the inclined shapes for the patterned second polycrystalline-silicon layers 111b, and thereafter, an intergate-dielectric layer (ONO) 112 is deposited over the patterned second polycrystalline-silicon layers 111b and the exposed planarized field-oxide layers 104a, as shown in FIG. 2B; and a planarized third polycrystalline-silicon layer 113a is formed over the intergate-dielectric layer 112 by using CMP and a tungsten-disilicide (WSi2) layer 114 is then formed over the planarized third polycrystalline-silicon layer 113a, as shown in FIG. 2C. It is clearly seen from FIG. 2C that two critical masking photoresist steps are also required, the second masking photoresist step is also critical, and misalignment is inevitable. Moreover, although two corners of the patterned second conductive layer 111b are inclined, but the corner field-emission effect is inevitable.
It is, therefore, a major objective of the present invention to offer a self-aligned STI structure having a self-aligned floating-gate structure with a high coupling ratio by using only one masking photoresist step.